The Taiwan Semiconductor Manufacturing Company (TSMC) held its beam-lifting ceremony for a new 3-nanometer chip manufacturing plant in Taiwan today. The event, attended by Taiwan’s economic minister and other guests, saw TSMC’s chairman Dr. Mark Liu share essential details for the company’s latest technology, a day after the industry was rife with reports that TSMC’s manufacturing plant for the next generation 2-nanometer chip process might be delayed. The executive informed observers that according to his company’s estimates, not only is the 3-nanometer process a $1.5 trillion product, but its yield rate is also equivalent to the 5-nanometer process technology.
TSMC Chairman Asserts 3-nanometer Will Increase Density By 60% & Reduce Power Consumption By Up To 35%
Today’s event was the first time that TSMC has celebrated the mass production of a manufacturing process, and it comes at a time when not only is the company facing a painful industry slowdown but also while critical voices in Taiwan are raising questions on whether it plans to move out of the region altogether. TSMC held the ceremony at Taiwan’s Tainan region, where it operates two twelve-inch wafer GIGAFABs. Specifically, the event was held at TSMC’s Fab 18, where it added another factor to the facility that is dedicated to producing the 3-nanometer chips. TSMC’s chairman Dr. Mark Liu shared that the clean room of each of these facilities is 58,000 meters squared in area, which is twice the size of a typical logic foundry. He also asserted that the 3-nanometer process is not showing any yield problems, with the yield having exceeded that of the 5-nanometer when it had entered mass production. The executive outlined that in terms of performance, chips built by the process will deliver 60% more logic density and up to 35% of reduced power consumption (at the same frequency) compared to the 5-nanometer process technology. Additionally, his estimate of the total value of the new technology, which is the money its products will be, was stunning, as Dr. Liu shared that according to TSMC’s estimates, 3-nanometer will produce products valued at a whopping $1.5 trillion. While his speech did not share how long this will take, a press release from TSMC shared that the period is five years. TSMC still sells products made from technologies that debuted in the late 1990s, and the 28-nanometer technology released in 2011 still represents 10% of the firm’s revenue. Dr. Liu also provided details for TSMC’s 2-nanometer plants. According to him, these will be built in the Hsinchu and Taichung science parks, with six phases. Crucially, he stressed that all plants are progressing according to schedule, comments which came as a report from Taiwan’s Economic Daily News that was released early in the morning claimed that the 2-nanometer plant in Taichung has been delayed. This report shared that a delay in the review process by the Taichung city government and the appointment of a new director might postpone land acquisition for the 2-nanometer plant. The review was initially expected to take place in May next year, and the Economic Daily shared concerns that delays can also affect the 2-nanometer mass production schedule. TSMC is aiming at 2025 to produce the next-generation chips, with the first phase of the fabs slated to enter into construction next year. An official from the Science and Technology Administration shared that the environmental planning should be completed in March, making it too late to hand over the land in May. The review was expected to take place later this month, but since the Metropolitan Bureau is yet to take office, its timeline is now uncertain.
